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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [tags/] [Rev1/] [bench/] - Rev 92

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Rev Log message Author Age Path
89 unneback 5092d 16h /versatile_mem_ctrl/tags/Rev1/bench
82 mikaeljf 5150d 22h /versatile_mem_ctrl/trunk/bench
80 mikaeljf 5151d 20h /versatile_mem_ctrl/trunk/bench
75 mikaeljf 5204d 17h /versatile_mem_ctrl/trunk/bench
74 Minor update of rtl Makefile. mikaeljf 5208d 16h /versatile_mem_ctrl/trunk/bench
70 mikaeljf 5212d 01h /versatile_mem_ctrl/trunk/bench
69 mikaeljf 5212d 21h /versatile_mem_ctrl/trunk/bench
35 work for limited test case unneback 5233d 16h /versatile_mem_ctrl/trunk/bench
33 work for limited test case, no cke inhibit for fifo empty unneback 5233d 19h /versatile_mem_ctrl/trunk/bench
32 Updated the testbench to match the new wishbone interface. mikaeljf 5236d 23h /versatile_mem_ctrl/trunk/bench
29 Adapted the test bench to the new wishbone interface. mikaeljf 5242d 16h /versatile_mem_ctrl/trunk/bench
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5242d 18h /versatile_mem_ctrl/trunk/bench
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5271d 17h /versatile_mem_ctrl/trunk/bench
17 Modified rtl Makefile and tb_defines.v mikaeljf 5274d 16h /versatile_mem_ctrl/trunk/bench
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5275d 17h /versatile_mem_ctrl/trunk/bench
14 Added external feedback of DDR SDRAM clock. mikaeljf 5365d 19h /versatile_mem_ctrl/trunk/bench
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5365d 22h /versatile_mem_ctrl/trunk/bench
12 Minor update of whishbone FSMs in TB mikaeljf 5375d 23h /versatile_mem_ctrl/trunk/bench
11 Initial version with support for DDR mikaeljf 5376d 10h /versatile_mem_ctrl/trunk/bench
10 unneback 5403d 18h /versatile_mem_ctrl/trunk/bench

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