URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [tags/] [Rev2/] [bench/] - Rev 109

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Rev	Log message	Author	Age	Path
109	Rev2 from trunk	unneback	4705d 01h	/versatile_mem_ctrl/tags/Rev2/bench
106	added texinfo User guide and updated fsm	unneback	4878d 16h	/versatile_mem_ctrl/trunk/bench
99	updated stimuli with automatic check	unneback	4917d 00h	/versatile_mem_ctrl/trunk/bench
94	new TB	unneback	5064d 02h	/versatile_mem_ctrl/trunk/bench
82		mikaeljf	5133d 05h	/versatile_mem_ctrl/trunk/bench
80		mikaeljf	5134d 03h	/versatile_mem_ctrl/trunk/bench
75		mikaeljf	5187d 00h	/versatile_mem_ctrl/trunk/bench
74	Minor update of rtl Makefile.	mikaeljf	5190d 23h	/versatile_mem_ctrl/trunk/bench
70		mikaeljf	5194d 08h	/versatile_mem_ctrl/trunk/bench
69		mikaeljf	5195d 04h	/versatile_mem_ctrl/trunk/bench
35	work for limited test case	unneback	5215d 23h	/versatile_mem_ctrl/trunk/bench
33	work for limited test case, no cke inhibit for fifo empty	unneback	5216d 02h	/versatile_mem_ctrl/trunk/bench
32	Updated the testbench to match the new wishbone interface.	mikaeljf	5219d 06h	/versatile_mem_ctrl/trunk/bench
29	Adapted the test bench to the new wishbone interface.	mikaeljf	5224d 23h	/versatile_mem_ctrl/trunk/bench
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5225d 01h	/versatile_mem_ctrl/trunk/bench
18	Updated the rtl/verilog Makefile and the bench Makefile.	mikaeljf	5254d 00h	/versatile_mem_ctrl/trunk/bench
17	Modified rtl Makefile and tb_defines.v	mikaeljf	5256d 23h	/versatile_mem_ctrl/trunk/bench
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5258d 00h	/versatile_mem_ctrl/trunk/bench
14	Added external feedback of DDR SDRAM clock.	mikaeljf	5348d 02h	/versatile_mem_ctrl/trunk/bench
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5348d 05h	/versatile_mem_ctrl/trunk/bench

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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [tags/] [Rev2/] [bench/] - Rev 109

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