URL https://opencores.org/ocsvn/vg_z80_sbc/vg_z80_sbc/trunk

Subversion Repositories vg_z80_sbc

[/] [vg_z80_sbc/] [trunk/] [rtl/] - Rev 35

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Rev	Log message	Author	Age	Path
35	New directory structure.	root	5600d 06h	/vg_z80_sbc/trunk/rtl
31	Remove 16550 UART from project.	hharte	5685d 09h	/trunk/rtl
30	Update top-level with new features, update comments, update backplane for front panel, and other peripherals.	hharte	5685d 09h	/trunk/rtl
29	Allow either Monitor 4.0C (serial) or 4.3 (Flashwriter2) to be used, depending on `define.	hharte	5685d 10h	/trunk/rtl
28	Initial Version, Front Panel (Programmed Output Port, and Sense Switches)	hharte	5685d 10h	/trunk/rtl
27	Clean up comments.	hharte	5685d 10h	/trunk/rtl
24	Fix dat width	hharte	5686d 19h	/trunk/rtl
23	Fix shifted keys, start adding support for ctrl keys.	hharte	5686d 19h	/trunk/rtl
22	Fix UART to work as Bitstreamer serial ports.	hharte	5686d 19h	/trunk/rtl
21	Update to latest version of wb_ddr from soc_lm32 project	hharte	5686d 19h	/trunk/rtl
20	Update to latest version of wb_ddr core from soc-lm32 project	hharte	5686d 19h	/trunk/rtl
19	Fix Address Width parameter	hharte	5686d 19h	/trunk/rtl
18	Fix incorrect first row of each character in first column.	hharte	5686d 20h	/trunk/rtl
17	Clean up comments/whitespace.	hharte	5692d 09h	/trunk/rtl
16	Boots Vector Graphic CP/M 2.2 from FLASH disk image. Added ISE Project files, MCS and BIT files for programming the FPGA.	hharte	5692d 14h	/trunk/rtl
13	Changed I/O addressing so addresses are not shifted left by two bits. Commented out DDR controller, and replaced with 8K of SRAM. Replaced FLASH memory interface with 4K SRAM. Added Vector HD/FD Disk Controller, using FLASH memory for storage. This design can now boot Vector Graphic 56K CP/M 2.2. But be aware that there is only 12K in the TPA, since the Spartan3E does not have enough block RAM to make more. This system is enough to test the Z80 core more thorougly. The EXZ80ALL.COM program on the included disk image tests all documented Z80 instructions. Some tests pass, some don't. This means there is more work to be done on the wb_z80 core.	hharte	5692d 14h	/trunk/rtl
12	Initial implementation of a Vector Graphic HD/FD Disk Controller with Wishbone interface. See the PDF in /doc for more information about this controller. For now, the storage is implemented in FLASH memory, which is read-only to the controller. Also, the controller does not check (CRC) the disk sector data, like the original does. Instead, it inserts 00's where the CRC goes, to simulate a correctly checked CRC. I am able to boot CP/M 2.2 using this controller, with the vgboot.mcs image programmed into FLASH. See the diskimage/ directory.	hharte	5692d 14h	/trunk/rtl
11	Fully parameterize so different size SRAMs can be instantiated.	hharte	5692d 14h	/trunk/rtl
10	Change address mapping for I/O cycles.	hharte	5692d 14h	/trunk/rtl
9	Change default mapping. Update address decoding for I/O Space.	hharte	5692d 14h	/trunk/rtl

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Subversion Repositories vg_z80_sbc

[/] [vg_z80_sbc/] [trunk/] [rtl/] - Rev 35

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