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[/] [xgate/] - Rev 61

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Rev Log message Author Age Path
61 Update to RISC block to fix DEBUG mode, testbench update rehayes 5217d 00h /xgate
60 Add ability at insert wait states on RAM access rehayes 5217d 00h /xgate
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5217d 00h /xgate
58 WISHBONE Bus update. rehayes 5269d 00h /xgate
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5269d 03h /xgate
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5285d 04h /xgate
55 Minor change to instruction set details. rehayes 5285d 04h /xgate
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5285d 04h /xgate
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5285d 04h /xgate
52 Minor changes to aide waveform debug rehayes 5285d 04h /xgate
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5301d 00h /xgate
50 incremental update to match status bit changes rehayes 5301d 00h /xgate
49 First pass with instruction set details rehayes 5301d 01h /xgate
48 Update for SBC ana ADC condition code changes rehayes 5301d 01h /xgate
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5301d 01h /xgate
46 Update to remove stack registers and add new register text. rehayes 5332d 23h /xgate
45 Update to remove stack registers and add new register text. rehayes 5332d 23h /xgate
44 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5334d 22h /xgate
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5334d 22h /xgate
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5334d 22h /xgate

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