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[/] [xgate/] [trunk/] [bench/] - Rev 57

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Rev Log message Author Age Path
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5283d 15h /xgate/trunk/bench
50 incremental update to match status bit changes rehayes 5299d 12h /xgate/trunk/bench
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5334d 12h /xgate/trunk/bench
39 delete rehayes 5362d 16h /xgate/trunk/bench
37 RAM model breakout for testbench rehayes 5362d 17h /xgate/trunk/bench
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5362d 17h /xgate/trunk/bench
35 Add byte lane select input to all tasks rehayes 5362d 17h /xgate/trunk/bench
27 Subversion test, no actual code changes rehayes 5387d 10h /xgate/trunk/bench
21 Added timeout, total error count, and XGCHN test rehayes 5395d 12h /xgate/trunk/bench
20 Added event signal for compare error tracking in top level test bench. rehayes 5395d 12h /xgate/trunk/bench
19 Verilog memory image for testing rehayes 5395d 12h /xgate/trunk/bench
18 Complete XGCHN test code rehayes 5395d 12h /xgate/trunk/bench
13 Debug functions test code rehayes 5409d 12h /xgate/trunk/bench
11 Update with Single Step debuging test rehayes 5409d 12h /xgate/trunk/bench
10 Minor Cleanup rehayes 5414d 12h /xgate/trunk/bench
9 Update for new testbench usage rehayes 5415d 10h /xgate/trunk/bench
8 Clean up, Fix default ISR rehayes 5415d 10h /xgate/trunk/bench
7 Fix to take advantage of change to sconv program. rehayes 5421d 09h /xgate/trunk/bench
6 Update to create output file name from input file name by changing extension to .v rehayes 5421d 10h /xgate/trunk/bench
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5422d 12h /xgate/trunk/bench

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