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[/] [xgate/] [trunk/] [bench/] - Rev 70

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Rev Log message Author Age Path
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5178d 17h /xgate/trunk/bench
65 Parameterize delays based on number of RAM wait states. rehayes 5198d 13h /xgate/trunk/bench
62 Cleanup implicit wire declarations. rehayes 5208d 12h /xgate/trunk/bench
60 Add ability at insert wait states on RAM access rehayes 5215d 12h /xgate/trunk/bench
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5283d 16h /xgate/trunk/bench
50 incremental update to match status bit changes rehayes 5299d 12h /xgate/trunk/bench
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5334d 12h /xgate/trunk/bench
39 delete rehayes 5362d 16h /xgate/trunk/bench
37 RAM model breakout for testbench rehayes 5362d 17h /xgate/trunk/bench
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5362d 17h /xgate/trunk/bench
35 Add byte lane select input to all tasks rehayes 5362d 17h /xgate/trunk/bench
27 Subversion test, no actual code changes rehayes 5387d 10h /xgate/trunk/bench
21 Added timeout, total error count, and XGCHN test rehayes 5395d 12h /xgate/trunk/bench
20 Added event signal for compare error tracking in top level test bench. rehayes 5395d 12h /xgate/trunk/bench
19 Verilog memory image for testing rehayes 5395d 12h /xgate/trunk/bench
18 Complete XGCHN test code rehayes 5395d 12h /xgate/trunk/bench
13 Debug functions test code rehayes 5409d 12h /xgate/trunk/bench
11 Update with Single Step debuging test rehayes 5409d 12h /xgate/trunk/bench
10 Minor Cleanup rehayes 5414d 12h /xgate/trunk/bench
9 Update for new testbench usage rehayes 5415d 11h /xgate/trunk/bench

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