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[/] [xgate/] [trunk/] [rtl/] [verilog/] - Rev 62

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Rev Log message Author Age Path
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5245d 06h /xgate/trunk/rtl/verilog
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5297d 09h /xgate/trunk/rtl/verilog
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5313d 10h /xgate/trunk/rtl/verilog
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5329d 07h /xgate/trunk/rtl/verilog
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5363d 04h /xgate/trunk/rtl/verilog
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5363d 04h /xgate/trunk/rtl/verilog
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5364d 06h /xgate/trunk/rtl/verilog
40 Update for single program counter adder rehayes 5384d 09h /xgate/trunk/rtl/verilog
34 minor changes related to wishbone master interface rehayes 5392d 11h /xgate/trunk/rtl/verilog
31 Cleanup for MAX_CHANNEL bus rehayes 5404d 06h /xgate/trunk/rtl/verilog
30 Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus rehayes 5404d 06h /xgate/trunk/rtl/verilog
29 Added some constant assigments, still needs more work to complete rehayes 5404d 06h /xgate/trunk/rtl/verilog
28 Added comment line rehayes 5404d 06h /xgate/trunk/rtl/verilog
26 Add synopsys commands, add else defaults for semphore state machine. rehayes 5419d 07h /xgate/trunk/rtl/verilog
25 Fix connected net name rehayes 5419d 08h /xgate/trunk/rtl/verilog
24 Delete unused inputs rehayes 5419d 09h /xgate/trunk/rtl/verilog
17 Additions for XGCHID debug commands rehayes 5425d 06h /xgate/trunk/rtl/verilog
15 Fix R1 load at boot up, add debug features rehayes 5438d 04h /xgate/trunk/rtl/verilog
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5439d 06h /xgate/trunk/rtl/verilog
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5452d 07h /xgate/trunk/rtl/verilog

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