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[/] [xge_mac/] [trunk/] - Rev 28

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Rev Log message Author Age Path
28 Adding parameter for max frame size antanguay 4221d 11h /xge_mac/trunk
27 Fix octets stats on barrel shift transitions antanguay 4270d 10h /xge_mac/trunk
26 Fix packet count antanguay 4276d 11h /xge_mac/trunk
25 Timing improvements, reduced FIFO size from 1024 to 512 antanguay 4276d 12h /xge_mac/trunk
24 Use FIFO's for statistics clock domain crossing antanguay 4276d 14h /xge_mac/trunk
23 Adding basic packet stats antanguay 4276d 20h /xge_mac/trunk
22 Added prototype system verilog testbench antanguay 4278d 16h /xge_mac/trunk
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4278d 17h /xge_mac/trunk
20 Updates for Xilinx synthesis antanguay 4568d 11h /xge_mac/trunk
19 Updates for 32/64 bit systems antanguay 4743d 12h /xge_mac/trunk
18 Updates for linux 32-bit antanguay 4744d 09h /xge_mac/trunk
17 Fixed deprecated SystemC warnings antanguay 4746d 17h /xge_mac/trunk
16 Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim antanguay 4746d 23h /xge_mac/trunk
15 Updated for Verilator 3.813 antanguay 4765d 23h /xge_mac/trunk
14 Change interface to big endian, added serdes examples to testbench antanguay 5354d 18h /xge_mac/trunk
13 Change interface to big endian, added serdes examples to testbench antanguay 5354d 18h /xge_mac/trunk
12 Change interface to big endian, added serdes examples to testbench antanguay 5354d 19h /xge_mac/trunk
11 Fixed clock crossing antanguay 5460d 16h /xge_mac/trunk
10 Added details to spec antanguay 5558d 11h /xge_mac/trunk
7 New directory structure. root 5633d 04h /xge_mac/trunk

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