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[/] [xulalx25soc/] [trunk/] [rtl/] - Rev 91

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Rev	Log message	Author	Age	Path
90	Reads and writes to the SD over SPI port now work. The card appears, as of now, to be fully functional.	dgisselq	2967d 21h	/xulalx25soc/trunk/rtl
89	Bug fixes, following the adf_ce logic combining ALU/DIVIDE/FPU pipeline logic into one register, this fixes that logic so that instructions without their condition fulfilled are still "executed" and marked as done.	dgisselq	2967d 21h	/xulalx25soc/trunk/rtl
88	Adjusted copyright date.	dgisselq	2967d 21h	/xulalx25soc/trunk/rtl
87	Placed the interrupt into the carry chain for less logic area.	dgisselq	2967d 21h	/xulalx25soc/trunk/rtl
86	Fine tuning the `defines, so that you can build pipelined without pipelined bus access and so forth.	dgisselq	2967d 21h	/xulalx25soc/trunk/rtl
85	First version of the SD-SPI interface, with partial functionality. (No the empty link that was here before.)	dgisselq	2971d 18h	/xulalx25soc/trunk/rtl
84	First part of switching to proper sdspi.v, and not just the link.	dgisselq	2971d 18h	/xulalx25soc/trunk/rtl
83	Fixes a bug in the LX9 build whereby the flash was never ever granted permission to use the SPI port.	dgisselq	2972d 22h	/xulalx25soc/trunk/rtl
74	Adds the SD-card capability, and connects the debug wires to/from the uartdev in case it needs to be debugged.	dgisselq	2973d 17h	/xulalx25soc/trunk/rtl
73	Simplified logic.	dgisselq	2973d 17h	/xulalx25soc/trunk/rtl
72	Sets XULA25 as the default.	dgisselq	2973d 17h	/xulalx25soc/trunk/rtl
71	Needed to play with subtle timing to get this to build. Expect me to play with these two clock numbers more.	dgisselq	2973d 18h	/xulalx25soc/trunk/rtl
70	Cosmetic (minor) update.	dgisselq	2973d 18h	/xulalx25soc/trunk/rtl
69	Massive logic simplification. This is also the first (verified) working version.	dgisselq	2973d 18h	/xulalx25soc/trunk/rtl
68	Fixes the debug ack line, so it no longer acks when there isn't a dbg_stb. Fixed the multiply option parameter, so it sets a 3-clock multiply properly. Adjusted the watchdog timer so that it now produces a timer that doesn't reload--since this is pointless for a watchdog. Finally, connects a reset line to the DMA, to make certain that resetting the CPU will also reset any ongoing DMA operation.	dgisselq	2973d 18h	/xulalx25soc/trunk/rtl
67	Simplifies logic, and guarantees that the minimum set value will always produce an int. For example, if the count was X before, setting X-1 wouldn't produce an interrupt since it had passed. Now it produces an interrupt, and keeps the next interrupt valid.	dgisselq	2973d 18h	/xulalx25soc/trunk/rtl
66	Simplified logic (barely).	dgisselq	2973d 18h	/xulalx25soc/trunk/rtl
65	Makes the auto-reload feature a parameterized (generic) feature, so the same code will work for both auto-reloadable and non-autoreloadable (i.e. watchdog) timers.	dgisselq	2973d 18h	/xulalx25soc/trunk/rtl
64	First (verified) working version.	dgisselq	2973d 18h	/xulalx25soc/trunk/rtl
63	Simplified logic.	dgisselq	2973d 18h	/xulalx25soc/trunk/rtl

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[/] [xulalx25soc/] [trunk/] [rtl/] - Rev 91

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