Rev |
Log message |
Author |
Age |
Path |
78 |
Comments out the line that caused a compiler warning--setting an unused
variable. Code should be better as a result. |
dgisselq |
3023d 15h |
/xulalx25soc/trunk/sw |
77 |
Adds register names and values for the SD card interface. |
dgisselq |
3023d 15h |
/xulalx25soc/trunk/sw |
76 |
Now tries to avoid reading from the stack if the stack addresses are already
known to be bad. That way, the debugger tries to preserve any bus error address
already on the buserr device. |
dgisselq |
3023d 15h |
/xulalx25soc/trunk/sw |
53 |
Added a touch of error checking. |
dgisselq |
3071d 16h |
/xulalx25soc/trunk/sw |
49 |
Added some documentation to make the read and write calls easier to understand. |
dgisselq |
3099d 18h |
/xulalx25soc/trunk/sw |
46 |
This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles. |
dgisselq |
3101d 19h |
/xulalx25soc/trunk/sw |
42 |
Minor changes. |
dgisselq |
3105d 15h |
/xulalx25soc/trunk/sw |
41 |
Bug fix. This was preventing dumpsdram from accurately reading back what
had been written to the RAM earlier. |
dgisselq |
3105d 15h |
/xulalx25soc/trunk/sw |
40 |
This adds to dumpsdram the capability to run over a port, such as with
busmaster_tb. |
dgisselq |
3107d 02h |
/xulalx25soc/trunk/sw |
38 |
Updated to remove the build dependence upon ZipCPU. |
dgisselq |
3109d 01h |
/xulalx25soc/trunk/sw |
33 |
Oops -- the audio was wired audio first then the interrupt controller, not
the other way around. This adjusts regdefs to match what's on the chip. |
dgisselq |
3113d 18h |
/xulalx25soc/trunk/sw |
31 |
A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25. |
dgisselq |
3113d 18h |
/xulalx25soc/trunk/sw |
30 |
Bug fixes. In particular, this fixes a segmentation violation. |
dgisselq |
3113d 22h |
/xulalx25soc/trunk/sw |
29 |
This adds a vastly updated and superious ziprun capability to the repository.
ziprun now accepts ELF program files *only*, reads them, and places them onto
the board. This includes the ability, within the ELF file, of specifying
whether or not the data is sent to block ram, SD ram, or Flash, as well as
the ability of specifying the initial address. (Of course, that's a one time
thing--to always have the same initial address, set the address in
rtl/busmaster.v) |
dgisselq |
3114d 14h |
/xulalx25soc/trunk/sw |
28 |
Oops--two files needed by zipdbg weren't originally placed in the directory. |
dgisselq |
3114d 19h |
/xulalx25soc/trunk/sw |
25 |
Fixing compile time warnings. |
dgisselq |
3114d 19h |
/xulalx25soc/trunk/sw |
24 |
Added the #define necessary to enable (and clear) SCOPE interrupts. |
dgisselq |
3120d 17h |
/xulalx25soc/trunk/sw |
17 |
Some basic updates, to include adding in a missing file (zipstate). Most of
these updates include making sure that the XuLA2 device can be accessed via
the USB. (Prior versions accessed the FPGA via serial port or network ...) |
dgisselq |
3179d 19h |
/xulalx25soc/trunk/sw |
13 |
This version is now working. (It probably would've worked before, but
everything is now working.) |
dgisselq |
3181d 14h |
/xulalx25soc/trunk/sw |
11 |
Getting software up and running on the board for the first time. (Not there
yet, but I think these items have now proven themselves.) |
dgisselq |
3181d 17h |
/xulalx25soc/trunk/sw |