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121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.
mohor 7598d 04h /
120 This commit was manufactured by cvs2svn to create tag 'rel_15'. 7607d 01h /
119 Artisan RAMs added. mohor 7607d 01h /
118 Artisan RAM fixed (when not using BIST). mohor 7607d 01h /
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.
mohor 7607d 01h /
116 This commit was manufactured by cvs2svn to create tag 'rel_14'. 7612d 19h /
115 Artisan ram instances added. simons 7612d 19h /
114 This commit was manufactured by cvs2svn to create tag 'rel_13'. 7639d 20h /
113 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7639d 20h /
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7639d 20h /
111 Fixed according to the linter.
Case statement for data_out joined.
mohor 7641d 20h /
110 Fixed according to the linter. mohor 7641d 20h /
109 Fixed according to the linter. mohor 7641d 21h /
108 Fixed according to the linter. mohor 7641d 22h /
107 Fixed according to the linter. mohor 7641d 22h /
106 Unused signal removed. mohor 7647d 20h /
105 This commit was manufactured by cvs2svn to create tag 'rel_11'. 7648d 09h /
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.
tadejm 7648d 09h /
103 This commit was manufactured by cvs2svn to create tag 'complete_1'. 7651d 00h /
102 Little fixes (to fix warnings). mohor 7651d 00h /

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