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Rev Log message Author Age Path
116 Update documentation to reflect the latest core updates. olivier.girard 4768d 07h /
115 Add linker script example. olivier.girard 4777d 06h /
114 Improved the VerifyCPU_ID procedure. olivier.girard 4780d 06h /
113 Created ChangeLog files... olivier.girard 4781d 06h /
112 Modified comment. olivier.girard 4785d 05h /
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4786d 05h /
110 Rework of the GUI for the software development tools.
Added possibility to give custom information through the omsp_alias.xml file.		 olivier.girard 4787d 05h /
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4840d 14h /
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4842d 03h /
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4842d 03h /
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4842d 04h /
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4857d 05h /
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4861d 06h /
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 4862d 11h /
102 Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:

- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+		 olivier.girard 4863d 04h /
101 Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. olivier.girard 4863d 06h /
100 Update HTML documentation with Actel's FPGA implementation example (file & directory description section). olivier.girard 4866d 05h /
99 Small fix for CVER simulator support. olivier.girard 4867d 06h /
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4867d 06h /
97 Update Tools' Windows executables with EraseROM command fix. olivier.girard 4868d 05h /

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