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61 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7937d 15h /
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7937d 15h /
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7937d 16h /
58 Removed all logic from asynchronous reset network mihad 7942d 17h /
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7942d 23h /
56 Number of state bits define was removed mihad 7943d 13h /
55 Changed state machine encoding to true one-hot mihad 7943d 14h /
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7976d 16h /
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7976d 19h /
52 Oops, never before noticed that OC header is missing mihad 7976d 23h /
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7976d 23h /
50 Got rid of undef directives mihad 7979d 16h /
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7979d 16h /
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7979d 16h /
47 Known issues repaired mihad 7979d 21h /
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 7984d 16h /
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7985d 21h /
44 Added for testing of Configuration Cycles Type 1 mihad 7985d 22h /
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 7985d 22h /
42 Removed out of date files mihad 7997d 22h /

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