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Rev Log message Author Age Path
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7970d 01h /
64 The testcase I just added in previous revision repaired mihad 7970d 03h /
63 Added additional testcase and changed rst name in BIST to trst mihad 7970d 05h /
62 Added BIST signals for RAMs. mihad 7972d 22h /
61 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7980d 22h /
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7980d 22h /
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7980d 23h /
58 Removed all logic from asynchronous reset network mihad 7986d 00h /
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7986d 06h /
56 Number of state bits define was removed mihad 7986d 20h /
55 Changed state machine encoding to true one-hot mihad 7986d 21h /
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8019d 23h /
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8020d 02h /
52 Oops, never before noticed that OC header is missing mihad 8020d 06h /
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8020d 06h /
50 Got rid of undef directives mihad 8022d 23h /
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8022d 23h /
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8022d 23h /
47 Known issues repaired mihad 8023d 05h /
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8027d 23h /

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