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[/] - Rev 95

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Rev Log message Author Age Path
95 Removed this file, because it was too large - long download time. mihad 7734d 06h /
94 Changed one critical PCI bus signal logic. mihad 7734d 06h /
93 Added a test application! mihad 7734d 13h /
92 Update! mihad 7734d 14h /
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7770d 03h /
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7770d 03h /
89 Burst 2 error fixed. mihad 7806d 04h /
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.
mihad 7812d 03h /
87 Updated acording to RTL changes. mihad 7824d 01h /
86 Entered the option to disable no response counter in wb master. mihad 7824d 01h /
85 Changed Vendor ID defines. mihad 7824d 05h /
84 Changed vendor ID. mihad 7827d 23h /
83 Cleaned up the code. No functional changes. mihad 7852d 22h /
82 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7866d 18h /
81 Updated synchronization in top level fifo modules. mihad 7866d 18h /
80 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7869d 23h /
79 Updated. mihad 7869d 23h /
78 Old files with wrong names removed. mihad 7869d 23h /
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7869d 23h /
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7872d 23h /

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