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21 Fix overrun and underrun interrupts bug

The overrun and underrun did not have any logic for
resetting their signals, this patch changes that so
that the interrupt signal is only on when the event
happens. The interrupt will be latched into
the interrupt status register anyway, so keeping it
high for (in worst case) one clock cycle is enough.
stekern 4724d 09h /
20 root 5521d 20h /
19 root 5577d 22h /
18 Added old uploaded documents to new repository. root 5578d 00h /
17 New directory structure. root 5578d 00h /
16 Fixed a bug in the IN-FIFO - 18 bit samples where not alligned correctly. rudi 7885d 18h /
15 Updated copyright header. rudi 7942d 05h /
14 Fixed a bug reported by Igor. Apparently this bug only shows up when
the WB clock is very low (2x bit_clk). Updated Copyright header.
rudi 7942d 05h /
13 Changed the datasheet and STATUS.txt rudi 7942d 05h /
12 - Added defines to select fifo depth between 4, 8 and 16 entries. rudi 8134d 08h /
11 - fixed spelling rudi 8140d 07h /
10 - Fixed the order of the thrash hold bits to match the spec.
- Many minor synthesis cleanup items ...
rudi 8140d 07h /
9 *** empty log message *** rudi 8160d 02h /
8 Simulation Makefile rudi 8160d 02h /
7 Added test bench for public release rudi 8160d 03h /
6 - Removed RTY_O output.
- Added Clock and Reset Inputs to documentation.
- Changed IO names to be more clear.
- Uniquifyed define names to be core specific.
rudi 8347d 03h /
5 Added Directory Tree Description to README file rudi 8350d 03h /
4 - Changed to new directory structure rudi 8354d 05h /
3 This commit was manufactured by cvs2svn to create tag 'start'. 8430d 09h /
2 Initial Checkin rudi 8430d 09h /

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