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Rev Log message Author Age Path
34 Corrected speed issues after rev 1.9 update. sybreon 6270d 12h /
33 Fixed minor data hazard bug spotted by Matt Ettus. sybreon 6285d 19h /
32 Modified compilation sequence. sybreon 6285d 19h /
31 Removed byte acrobatics. sybreon 6285d 19h /
30 Minor updates as sw/c/aeMB_testbench.c got updated. sybreon 6288d 20h /
29 Added code documentation.
Added new tests that test floating point, modulo arithmetic and multiplication/division.
sybreon 6288d 20h /
28 Fixed simulation bug. sybreon 6288d 20h /
27 Removed some unnecessary bubble control. sybreon 6289d 07h /
26 Fixed minor synthesis bug. sybreon 6289d 07h /
25 Added code documentation.
Improved size & speed of rtl/verilog/aeMB_aslu.v
sybreon 6289d 10h /
24 Made minor performance optimisations. sybreon 6289d 20h /
23 Fixed minor simulation bug. sybreon 6290d 12h /
22 Added support for 8-bit and 16-bit data types. sybreon 6290d 13h /
21 Added hierarchy block diagram. sybreon 6300d 18h /
20 Added basic documentation doc/aeMB_datasheet.pdf sybreon 6301d 08h /
19 Added initial unified memory core. sybreon 6302d 22h /
18 Moved testbench into /sim/verilog.
Simulation cleanups.
sybreon 6303d 15h /
17 Cosmetic changes sybreon 6304d 18h /
16 Added pipeline stalling from incomplete bus cycles.
Separated sync and async portions of code.
sybreon 6305d 06h /
15 Removed ROM file. Please generate it from the SW directory. sybreon 6311d 21h /

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