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Subversion Repositories altor32

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Rev Log message Author Age Path
18 - Fixed sign extension handling of some l.sf**ui instructions. ultra_embedded 4513d 08h /
17 - Option to specify IRQ vector offset. ultra_embedded 4516d 08h /
16 - Clean-up. ultra_embedded 4516d 08h /
15 - Improved peripheral register interface.
- Papilio XC3S250E FPGA project now uses pipelined core @ 32MHz.		 ultra_embedded 4516d 15h /
14 Added initial version of pipelined AltOR32 core. ultra_embedded 4516d 19h /
13 Fixed l.lhs sign extension bug.
Removed duplicate instruction definitions.		 ultra_embedded 4522d 19h /
12 - Removed broken memory stall signal support on basic implementation. ultra_embedded 4536d 08h /
11 - Added missing library file. ultra_embedded 4537d 11h /
10 - Added example Papilio One (XC3S250E) project.
Contains bootloader accessible via USB uart @ 115200.		 ultra_embedded 4537d 11h /
9 - Added bin->Xilinx blockRAM init tool. ultra_embedded 4537d 11h /
8 - Added X-Modem bootloader ultra_embedded 4537d 11h /
7 - Fixed verilator makefile. ultra_embedded 4537d 11h /
6 - Simplified interrupt handling
- Added optional boot address argument		 ultra_embedded 4537d 11h /
5 Added verilator simulation.
Added basic peripherals & soc.		 ultra_embedded 4539d 07h /
4 Added initial basic core RTL implementation (non-pipelined). ultra_embedded 4539d 07h /
3 Added top level makefile.
Builds simulator & executes basic test image.		 ultra_embedded 4543d 12h /
2 Added a simple simulator for OpenRisc 1000, where only the essential instructions have been implemented.

Runs code compiled with the following flags:
-msoft-div -msoft-float -msoft-mul -mno-ror -mno-cmov -mno-sext		 ultra_embedded 4543d 13h /
1 The project and the structure was created root 4544d 10h /

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