| Rev |
Log message |
Author |
Age |
Path |
| 21 |
Added synthesis files for Vivado. The RTL have not yet been updated with the latest changes available in the Quartus version. |
daniel.kho |
3830d 10h |
/ |
| 20 |
Updated simulation scripts. |
daniel.kho |
3830d 10h |
/ |
| 19 |
Updated synthesis constraints and scripts. |
daniel.kho |
3830d 10h |
/ |
| 18 |
Added hardware PRBS generator, modularised top-level by having separate file as the tester. |
daniel.kho |
3830d 10h |
/ |
| 17 |
Added more pipelining, enhancements. Tested on BeMicro kit. |
daniel.kho |
3830d 11h |
/ |
| 16 |
Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. |
daniel.kho |
3933d 07h |
/ |
| 15 |
[minor]: cleaned up sources. |
daniel.kho |
3935d 13h |
/ |
| 14 |
Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. |
daniel.kho |
3944d 04h |
/ |
| 13 |
Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. |
daniel.kho |
3944d 08h |
/ |
| 12 |
Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources. |
daniel.kho |
3953d 13h |
/ |
| 11 |
Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. |
daniel.kho |
3955d 07h |
/ |
| 10 |
Written a few more directed testcases (in user.vhdl), and fixed several bugs. TODO move the testcases to the stimuli folder. |
daniel.kho |
3959d 07h |
/ |
| 9 |
Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. |
daniel.kho |
3962d 03h |
/ |
| 8 |
[minor]: removed writeStream(). The write() procedure can be used for both stream and non-stream interfaces. For stream interfaces, just map the address argument to don't-cares. Made several other minor enhancements, simplifications. |
daniel.kho |
4062d 09h |
/ |
| 7 |
[minor]: renamed axi4-stream-bfm.vhdl to axi4-stream-bfm-master.vhdl so as to allow a future implementation of the AXI4-Stream slave / receiver. Changed simulation script to start GUI simulation only when there are no errors (previously, it brings up the GUI even when there are compilation errors). |
daniel.kho |
4066d 03h |
/ |
| 6 |
[minor]: expanded some waveforms and show random stimulus from simulation script. |
daniel.kho |
4066d 08h |
/ |
| 5 |
[minor]: refactored type names to use the convention 't_*' for more clarity. AXI4-Stream signal names also starts with a 't'. |
daniel.kho |
4066d 12h |
/ |
| 4 |
[minor]: Removed unused libraries from simulation script. |
daniel.kho |
4067d 06h |
/ |
| 3 |
Updated user.vhdl to use math_real's uniform for testbench randomisation. This is to avoid having to include third-party libraries into the project. Simulation of user.vhdl works - writeStream() procedure is used to send AXI4-Stream bus writes. More verification will follow. |
daniel.kho |
4067d 07h |
/ |
| 2 |
Initial commit.
Added packages and usage example for AXI4-Stream protocol.
Added simulation scripts for ModelSim/QuestaSim. |
daniel.kho |
4067d 17h |
/ |
