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Rev	Log message	Author	Age	Path
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7767d 17h	/
103	This commit was manufactured by cvs2svn to create tag 'complete_1'.		7770d 07h	/
102	Little fixes (to fix warnings).	mohor	7770d 07h	/
101	This commit was manufactured by cvs2svn to create tag 'rel_10'.		7774d 09h	/
100	Synchronization changed.	mohor	7774d 09h	/
99	PCI_BIST replaced with CAN_BIST.	mohor	7774d 09h	/
98	This commit was manufactured by cvs2svn to create tag 'rel_9'.		7779d 21h	/
97	Overrun fifo implemented with FFs, because it is not possible to create such a memory.	simons	7779d 21h	/
96	This commit was manufactured by cvs2svn to create tag 'rel_8'.		7779d 22h	/
95	Virtual silicon ram instances added.	simons	7779d 22h	/
94	This commit was manufactured by cvs2svn to create tag 'rel_7'.		7785d 09h	/
93	synthesis full_case parallel_case fixed.	mohor	7785d 09h	/
92	clkout is clk/2 after the reset.	mohor	7785d 17h	/
91	This commit was manufactured by cvs2svn to create tag 'rel_6'.		7786d 07h	/
90	paralel_case and full_case compiler directives added to case statements.	mohor	7786d 07h	/
89	This commit was manufactured by cvs2svn to create tag 'rel_5'.		7787d 04h	/
88	Previous change removed. When resynchronization occurs we go to seg1 stage. sync stage does not cause another start of seg1 stage.	mohor	7787d 04h	/
87	When hard_sync or resync occure we need to go to seg1 segment. Going to sync segment is in that case blocked.	mohor	7787d 04h	/
86	This commit was manufactured by cvs2svn to create tag 'rel_4'.		7788d 20h	/
85	Typo fixed.	mohor	7788d 20h	/

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