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Rev Log message Author Age Path
157 In "Extended mode" when dual filter was used and standard frame received,
upper nibble of the data was not filtered ok.		 igorm 7052d 17h /
156 Wake-up interrupt was generated in some cases. igorm 7073d 15h /
155 rd_info_pointer fixed (fifo_empty was used instead of info_empty). igorm 7081d 21h /
154 irq is cleared after the release_buffer command. This bug was entered with
changes for the edge triggered interrupts.		 igorm 7181d 15h /
153 Arbitration capture register changed. SW reset (setting the reset_mode bit)
doesn't work as HW reset.		 igorm 7189d 10h /
152 Fixes for compatibility after the SW reset. igorm 7193d 17h /
151 When CAN was reset by setting the reset_mode signal in mode register, it
was possible that CAN was blocked for a short period of time. Problem
occured very rarly.		 igorm 7196d 11h /
150 This commit was manufactured by cvs2svn to create tag 'rel_24'. 7215d 11h /
149 Fixed synchronization problem in real hardware when 0xf is used for TSEG1. igorm 7215d 11h /
148 This commit was manufactured by cvs2svn to create tag 'rel_23'. 7217d 18h /
147 Interrupt is always cleared for one clock after the irq register is read.
This fixes problems when CPU is using IRQs that are edge triggered.		 igorm 7217d 18h /
146 This commit was manufactured by cvs2svn to create tag 'rel_22'. 7217d 23h /
145 Arbitration bug fixed. igorm 7217d 23h /
144 This commit was manufactured by cvs2svn to create tag 'rel_21'. 7364d 15h /
143 Bit acceptance_filter_mode was inverted. igorm 7364d 15h /
142 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7383d 14h /
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7383d 14h /
140 I forgot to thange one signal name. igorm 7438d 12h /
139 Signal bus_off_on added. igorm 7438d 12h /
138 Header changed. Address latched to posedge. bus_off_on signal added. mohor 7477d 15h /

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