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Rev Log message Author Age Path
28 no message bbeaver 8319d 18h /
27 no message bbeaver 8320d 18h /
26 no message bbeaver 8321d 17h /
25 no message bbeaver 8322d 18h /
24 no message bbeaver 8324d 20h /
23 no message bbeaver 8325d 19h /
22 no message bbeaver 8325d 23h /
21 Added bookmarks. lampret 8326d 12h /
20 Some minor fixes. Document is now official version. lampret 8326d 13h /
19 no message bbeaver 8327d 20h /
18 no message bbeaver 8328d 18h /
17 Fixed link to specification_template.dot lampret 8329d 02h /
16 Added updated opencores coding guidelines. Added ver_plan.pdf and Specification template for Word. lampret 8329d 03h /
15 no message bbeaver 8349d 00h /
14 adding beginning LPM files bbeaver 8360d 20h /
13 This commit was manufactured by cvs2svn to create tag 'initial'. 8366d 20h /
12 Major cleanup.
Files are now compliant to Altera & Xilinx memories.
Memories are now compatible, i.e. drop-in replacements.
Added synthesizeable generic FPGA description.
Created "generic_memories" cvs entry.
rherveille 8366d 20h /
11 no message bbeaver 8373d 19h /
10 no message bbeaver 8373d 19h /
9 no message bbeaver 8377d 17h /

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