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43 This commit was manufactured by cvs2svn to create tag 'rel_19'. 8087d 12h /
42 This commit was manufactured by cvs2svn to create tag 'rel_12'. 8087d 12h /
41 Changed synthesizeable FPGA memory implementation.
Fixed some issues with Xilinx BlockRAM
rherveille 8087d 12h /
40 Updated PDF. lampret 8131d 14h /
39 Added Richard's feedback. lampret 8133d 15h /
38 Undeleted mohor 8154d 04h /
37 no message bbeaver 8390d 10h /
36 minor changes: unified with all common rams samg 8410d 19h /
35 corrected output: output not valid if ce low samg 8411d 00h /
34 added valid checks to behvioral model samg 8411d 01h /
33 added checks and task in behavioral section samg 8412d 02h /
32 no message bbeaver 8413d 07h /
31 no message bbeaver 8417d 08h /
30 no message bbeaver 8418d 06h /
29 got timing checks mostly correct
No functional stuff yet
bbeaver 8418d 07h /
28 no message bbeaver 8419d 07h /
27 no message bbeaver 8420d 07h /
26 no message bbeaver 8421d 06h /
25 no message bbeaver 8422d 08h /
24 no message bbeaver 8424d 09h /

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