OpenCores
URL https://opencores.org/ocsvn/cpu_lecture/cpu_lecture/trunk

Subversion Repositories cpu_lecture

[/] - Rev 25

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
25 uart transmitter state handling improved jsauermann 5180d 02h /
24 write updated SP in interrupt opcode jsauermann 5204d 01h /
23 fixed bugs in interrupt vector jsauermann 5205d 04h /
22 aligned I/O port numbers to real mega8 jsauermann 5205d 09h /
21 fixed bug in Sign bit computation for SUB and CP instructions jsauermann 5207d 03h /
20 readability of 95xx instructions improved jsauermann 5239d 00h /
19 another bug in the decoding of two-cycle instructions fixed jsauermann 5239d 00h /
18 fixed a bug that caused double execution of some 95xx instructions jsauermann 5242d 03h /
17 fixed missing carry flag for ROR instruction jsauermann 5246d 01h /
16 fixed missing RD_M signal for IN instruction jsauermann 5255d 02h /
15 fixed SP auto inc/dec problem jsauermann 5255d 04h /
14 fixed wrong Q_RSEL for LDD instruction jsauermann 5257d 00h /
13 fixed fault in LDD/STD decoding jsauermann 5258d 00h /
12 fixed bug in decoding of I/O address for SP jsauermann 5259d 01h /
11 fixed fault is BSET/BCLR instruction jsauermann 5261d 01h /
10 wait decoder fault fixed jsauermann 5261d 06h /
9 renamed 'main' to 'hello' in build commands jsauermann 5262d 02h /
8 picture quality slightly improved jsauermann 5262d 07h /
7 support multiple port sizes in make_mem jsauermann 5262d 08h /
6 support multiple port sizes in make_mem jsauermann 5262d 08h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.