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51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7942d 01h /
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 7942d 02h /
49 This commit was manufactured by cvs2svn to create tag 'sdram_test_working'. 8097d 13h /
48 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8097d 13h /
47 mon_cntl_o signals that controls monitor mux added. mohor 8097d 13h /
46 Asynchronous reset used instead of synchronous. mohor 8105d 19h /
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8112d 15h /
44 Signal names changed to lower case. mohor 8112d 15h /
43 Intentional error removed. mohor 8117d 15h /
42 A block for checking possible simulation/synthesis missmatch added. mohor 8117d 17h /
41 Function changed to logic because of some synthesis warnings. mohor 8125d 14h /
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8139d 14h /
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8140d 15h /
38 Few outputs for boundary scan chain added. mohor 8153d 13h /
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8153d 17h /
36 Structure changed. Hooks for jtag chain added. mohor 8157d 12h /
35 Dbg support datasheet added to cvs. mohor 8181d 17h /
34 Product brief added to cvs. mohor 8182d 11h /
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8187d 16h /
32 Stupid bug that was entered by previous update fixed. mohor 8188d 14h /

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