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Rev Log message Author Age Path
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7876d 07h /
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7876d 07h /
238 Defines fixed to use generic RAM by default. mohor 7888d 11h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7890d 17h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7890d 17h /
235 rev 4. mohor 7891d 07h /
234 Figure list assed to the revision 3. mohor 7891d 16h /
233 Revision 0.3 released. Some figures added. mohor 7891d 16h /
232 fpga define added. mohor 7896d 11h /
231 Description of Core Modules added (figure). mohor 7898d 12h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7902d 09h /
229 case changed to casex. mohor 7902d 09h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7902d 13h /
227 Changed BIST scan signals. tadejm 7902d 13h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7902d 14h /
225 Some minor changes. tadejm 7902d 14h /
224 Signals for a wave window in Modelsim. tadejm 7902d 16h /
223 Some code changed due to bug fixes. tadejm 7902d 16h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7906d 14h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7906d 14h /

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