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[/] - Rev 351

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Rev Log message Author Age Path
351 Turn defines into parameters in eth_cop olof 4714d 22h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4714d 23h /
349 Make all parameters configurable from top level olof 4715d 23h /
348 Added option to dump VCD files olof 4716d 22h /
347 Added information about running with Icarus Verilog olof 4716d 23h /
346 Updated project location olof 4717d 01h /
345 Temporarily disable failing tests olof 4717d 03h /
344 bit 9 in phy control register is self clearing olof 4723d 05h /
343 Address miss should not be asserted on short frames olof 4727d 01h /
342 Added cast to avoid inequality when comparing different data types olof 4727d 01h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4727d 01h /
340 Don't fail if log dir already exists olof 4727d 22h /
339 Added basic support for Icarus Verilog olof 4728d 22h /
338 root 5521d 03h /
337 root 5577d 05h /
336 Added old uploaded documents to new repository. root 5578d 09h /
335 New directory structure. root 5578d 09h /
334 Minor fixes for Icarus simulator. igorm 7026d 11h /
333 Some small fixes + some troubles fixed. igorm 7026d 23h /
332 Case statement improved for synthesys. igorm 7040d 04h /

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