OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 352

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
352 Removed delayed assignments from rtl code olof 4706d 07h /
351 Turn defines into parameters in eth_cop olof 4714d 21h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4714d 22h /
349 Make all parameters configurable from top level olof 4715d 22h /
348 Added option to dump VCD files olof 4716d 21h /
347 Added information about running with Icarus Verilog olof 4716d 22h /
346 Updated project location olof 4717d 00h /
345 Temporarily disable failing tests olof 4717d 01h /
344 bit 9 in phy control register is self clearing olof 4723d 04h /
343 Address miss should not be asserted on short frames olof 4726d 23h /
342 Added cast to avoid inequality when comparing different data types olof 4727d 00h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4727d 00h /
340 Don't fail if log dir already exists olof 4727d 21h /
339 Added basic support for Icarus Verilog olof 4728d 21h /
338 root 5521d 02h /
337 root 5577d 04h /
336 Added old uploaded documents to new repository. root 5578d 07h /
335 New directory structure. root 5578d 08h /
334 Minor fixes for Icarus simulator. igorm 7026d 10h /
333 Some small fixes + some troubles fixed. igorm 7026d 21h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.