URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 360

Rev	Log message	Author	Age	Path
360	Added partial implementation of the debug register from ORPSoC	olof	4696d 08h	/
359	Verilator linting fixes	olof	4698d 10h	/
358	Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version	olof	4700d 00h	/
357	Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC	olof	4700d 01h	/
356	Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure	olof	4700d 02h	/
355	Import Julius Baxter's verilator hints from ORPSoC	olof	4700d 03h	/
354	Whitespace cleanup	olof	4700d 04h	/
353	Inherit fixes for bit width of constants from ORPSoC	olof	4702d 05h	/
352	Removed delayed assignments from rtl code	olof	4706d 11h	/
351	Turn defines into parameters in eth_cop	olof	4715d 01h	/
350	Turn M[1-2]_ADDRESSED_S[1-2] defines into wires	olof	4715d 01h	/
349	Make all parameters configurable from top level	olof	4716d 02h	/
348	Added option to dump VCD files	olof	4717d 01h	/
347	Added information about running with Icarus Verilog	olof	4717d 02h	/
346	Updated project location	olof	4717d 04h	/
345	Temporarily disable failing tests	olof	4717d 05h	/
344	bit 9 in phy control register is self clearing	olof	4723d 07h	/
343	Address miss should not be asserted on short frames	olof	4727d 03h	/
342	Added cast to avoid inequality when comparing different data types	olof	4727d 03h	/
341	Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short	olof	4727d 04h	/