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Rev Log message Author Age Path
45 Added slave address configurability rherveille 7494d 13h /
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7579d 16h /
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7579d 16h /
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7589d 13h /
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7589d 13h /
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7589d 13h /
39 Forgot an 'end if' :-/ rherveille 7609d 09h /
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7612d 17h /
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7649d 09h /
36 Fixed cmd_ack generation item (no bug). rherveille 7764d 09h /
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7798d 00h /
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7801d 22h /
33 Fixed a bug in the Command Register declaration. rherveille 7824d 07h /
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7834d 07h /
31 Core is now a Multimaster I2C controller. rherveille 7838d 08h /
30 Small code simplifications rherveille 7838d 08h /
29 Core is now a Multimaster I2C controller rherveille 7838d 09h /
28 *** empty log message *** rherveille 7864d 02h /
27 Cleaned up code rherveille 7864d 02h /
26 *** empty log message *** rherveille 7867d 09h /

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