OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] - Rev 59

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
59 fixed short scl high pulse after clock stretch rherveille 6608d 23h /
58 fixed (n)ack generation rherveille 6641d 01h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal		 rherveille 6641d 01h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.		 rherveille 7193d 22h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.		 rherveille 7195d 01h /
54 Fixed scl, sda delay. rherveille 7195d 01h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7490d 22h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7490d 23h /
51 Fixed simulation issue when writing to CR register rherveille 7545d 00h /
50 *** empty log message *** rherveille 7559d 18h /
49 Added testbench rherveille 7559d 18h /
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7561d 02h /
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7569d 22h /
46 Fixed slave address MSB='1' bug rherveille 7644d 23h /
45 Added slave address configurability rherveille 7644d 23h /
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7730d 02h /
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7730d 02h /
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7739d 23h /
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7739d 23h /
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7739d 23h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.