OpenCores
URL https://opencores.org/ocsvn/miniuart2/miniuart2/trunk

Subversion Repositories miniuart2

[/] - Rev 23

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
23 This commit was generated by cvs2svn to compensate for changes in r22, which
included commits to RCS files with non-trunk default branches.
philippe 7971d 16h /
22 no message philippe 7971d 16h /
21 This commit was manufactured by cvs2svn to create branch 'avendor'. 7971d 16h /
20 This commit was generated by cvs2svn to compensate for changes in r19, which
included commits to RCS files with non-trunk default branches.
philippe 7971d 16h /
19 no message philippe 7971d 16h /
18 no message philippe 7974d 16h /
17 Header and formating modif
modif on line 81: if (SampleCnt = 1 and BitPos >= 2) then -- Sample RxD on 1
philippe 7974d 16h /
16 Header and formating modif philippe 7974d 16h /
15 changed mail address philippe 8095d 16h /
14 no message philippe 8221d 20h /
13 no message philippe 8221d 20h /
12 Asserted TxD High on power on. (Added the line TxD <= '1').
Otherwise, the transmitter start with the Tx line low.
philippe 8221d 20h /
11 no message philippe 8264d 20h /
10 Prohibited SampleCnt to overflow over 3.
(This is just a security-not needed for the
design to reun correctly)
philippe 8264d 20h /
9 Corrected bug on LoadA signal in Txunit.vhd.
Load signal is now correctly sampled by BR_CLK.
philippe 8264d 20h /
8 Modified and detailed the Baudrate tolerance section philippe 8284d 18h /
7 no message philippe 8284d 18h /
6 Modified signal names to match port map philippe 8284d 18h /
5 no message philippe 8319d 18h /
4 This commit was manufactured by cvs2svn to create tag 'aversion'. 8319d 19h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.