| Rev |
Log message |
Author |
Age |
Path |
| 101 |
Documentation, wiki's address updated. |
rfajardo |
4652d 19h |
/ |
| 100 |
syn/altera/minsoc_top.qsf: I thought this file was being generated now as project file description. But it is merely a synthesis configuration file and must be here. File re-added. |
rfajardo |
4661d 17h |
/ |
| 99 |
backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. |
rfajardo |
4661d 17h |
/ |
| 98 |
Removing deprecated minsoc_top.qsf file. |
rfajardo |
4661d 17h |
/ |
| 97 |
As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. |
rfajardo |
4661d 17h |
/ |
| 96 |
Some files needed for Altera synthesis |
javieralso |
4662d 04h |
/ |
| 95 |
Makefile for Altera FPGAs fixed |
javieralso |
4663d 07h |
/ |
| 94 |
Fix bug in minsoc_top.prj for Altera synthesis |
javieralso |
4665d 16h |
/ |
| 93 |
Support for Altera synthesis. It needs some tune, but it works fine |
javieralso |
4665d 19h |
/ |
| 92 |
backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. |
rfajardo |
4666d 17h |
/ |
| 91 |
prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. |
rfajardo |
4666d 17h |
/ |
| 90 |
After minsoc_top.prj update, make regenerated src and xst files. |
rfajardo |
4667d 09h |
/ |
| 89 |
minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. |
rfajardo |
4667d 09h |
/ |
| 88 |
Project structure, Xilinx Makefiles and simulation working. |
rfajardo |
4667d 09h |
/ |
| 87 |
Synchronizing scripts to behave exactly the same. |
rfajardo |
4667d 10h |
/ |
| 86 |
Updating configure script messages. |
rfajardo |
4667d 10h |
/ |
| 85 |
Central project definition under prj. Synthesis and simulation take their project files from here. |
rfajardo |
4667d 11h |
/ |
| 84 |
syn/blackboxes/eth_top.v:
-module is now called ethmac instead of eth_top
-eth_defines.v is now called ethmac_defines.v |
rfajardo |
4668d 11h |
/ |
| 83 |
minsoc-install.sh: bzip2 program was being used, but its existance on target system was not being verified. It is now. |
rfajardo |
4679d 17h |
/ |
| 82 |
minsoc-install.sh: problems with copying the GNU Toolchain from download to tools. We uncompress the GNU Toolchain now once again to tools during the installation part. |
rfajardo |
4682d 16h |
/ |
