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Rev Log message Author Age Path
42 Added backpressure/stallability of output interface. mikel262 5396d 00h /
41 Fixed RLE ZRL bug occurring at end of 8x8 block mikel262 5533d 11h /
40 Fixed few bugs in BUF_FIFO and RLE encoder. mikel262 5576d 02h /
39 bug fix. mikel262 5579d 01h /
38 Reduced processing latency of Huffman encoding mikel262 5604d 01h /
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5608d 05h /
36 Fixed RLE ZRL bug. Added Chrominance Huffman tables. Fixed num encoded bytes bug. mikel262 5610d 01h /
35 Added check for image width in testbench. mikel262 5610d 13h /
34 Moved Quantizer to separate pipeline stage to balance processing chain load. mikel262 5610d 21h /
33 mikel262 5611d 06h /
32 mikel262 5612d 01h /
31 Specification update, minor area improvements in BUF_FIFO. mikel262 5615d 02h /
30 mikel262 5615d 15h /
29 mikel262 5615d 23h /
28 BU_FIFO SUB_RAM is now monolithic single block used by all SubFIFO - effect much less memory block usage. mikel262 5615d 23h /
27 mikel262 5618d 11h /
26 mikel262 5618d 12h /
25 moved from branch to trunk mikel262 5618d 12h /
24 mikel262 5618d 12h /
23 mikel262 5619d 22h /

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