URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 36

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4225d 18h	/
35	new test values, 1st exponentiation gives error on result with new pipeline commit for test purposes	JonasDC	4225d 20h	/
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4225d 21h	/
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4226d 00h	/
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4226d 01h	/
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4226d 06h	/
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4226d 07h	/
29	added software for generation of test input for the tesbenches	JonasDC	4226d 20h	/
28	updated makefile for new pipeline sources	JonasDC	4226d 21h	/
27	test input values for multiplier_tb	JonasDC	4226d 21h	/
26	testbench for only the montgommery multiplier	JonasDC	4226d 21h	/
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4226d 21h	/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4230d 06h	/
23	added descriptive comments	JonasDC	4230d 07h	/
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4233d 00h	/
21	changed x_i signal to xi	JonasDC	4234d 08h	/
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4234d 08h	/
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4239d 03h	/
18	updated stages with comments and renamed some signals for consistency	JonasDC	4240d 03h	/
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4240d 08h	/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories mod_sim_exp

[/] - Rev 36

Filtering Options