OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 53

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
53 correctly inferred ram for altera dual port ram JonasDC 4135d 18h /
52 correct inferring of blockram, no additional resources. JonasDC 4135d 18h /
51 true dual port ram for xilinx JonasDC 4135d 19h /
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx		 JonasDC 4135d 19h /
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.		 JonasDC 4147d 14h /
48 Tag of the starting version of the project JonasDC 4147d 14h /
47 added documentation for the IP core. JonasDC 4215d 19h /
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4215d 19h /
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4215d 19h /
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4219d 12h /
43 made the core parameters generics JonasDC 4219d 12h /
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4225d 20h /
41 removed deprecated files from version control JonasDC 4225d 20h /
40 adjusted core instantiation to new core module name JonasDC 4234d 00h /
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4234d 11h /
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4234d 17h /
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4238d 14h /
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4239d 10h /
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes		 JonasDC 4239d 13h /
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4239d 14h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.