OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 56

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
56 this is a branch to test performance of a new style of ram JonasDC 4126d 05h /
55 updated resource usage in comments JonasDC 4127d 02h /
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4127d 02h /
53 correctly inferred ram for altera dual port ram JonasDC 4127d 08h /
52 correct inferring of blockram, no additional resources. JonasDC 4127d 09h /
51 true dual port ram for xilinx JonasDC 4127d 10h /
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx		 JonasDC 4127d 10h /
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.		 JonasDC 4139d 05h /
48 Tag of the starting version of the project JonasDC 4139d 05h /
47 added documentation for the IP core. JonasDC 4207d 09h /
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4207d 10h /
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4207d 10h /
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4211d 03h /
43 made the core parameters generics JonasDC 4211d 03h /
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4217d 11h /
41 removed deprecated files from version control JonasDC 4217d 11h /
40 adjusted core instantiation to new core module name JonasDC 4225d 15h /
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4226d 02h /
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4226d 08h /
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4230d 05h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.