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Subversion Repositories mod_sim_exp

[/] - Rev 65

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Rev	Log message	Author	Age	Path
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4165d 17h	/
64	added synthesis reports of xilinx and altera	JonasDC	4165d 22h	/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4165d 22h	/
62	not used anymore	JonasDC	4166d 01h	/
61	updated comments, added optional altera constraint	JonasDC	4166d 01h	/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4168d 15h	/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4168d 16h	/
58	made fifo full a warning	JonasDC	4171d 16h	/
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4171d 16h	/
56	this is a branch to test performance of a new style of ram	JonasDC	4171d 19h	/
55	updated resource usage in comments	JonasDC	4172d 15h	/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4172d 16h	/
53	correctly inferred ram for altera dual port ram	JonasDC	4172d 22h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4172d 23h	/
51	true dual port ram for xilinx	JonasDC	4172d 23h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4172d 23h	/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4184d 18h	/
48	Tag of the starting version of the project	JonasDC	4184d 19h	/
47	added documentation for the IP core.	JonasDC	4252d 23h	/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4252d 23h	/

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[/] - Rev 65

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