OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] - Rev 165

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
165 fixed issues with PC relative fixups in the linker khays 4531d 00h /
164 Modified the data path to allow the bus to go idle while waiting for an interrupt. This makes it easier to debug code that uses the WAI instruction, as both Wr_Enable and Rd_Enable go low. jshamlet 4601d 11h /
163 sync with binutils 2.22.51.20111114 khays 4638d 23h /
162 Added optional generic to specify that the BRK instruction implements a WAit_for_Interrupt (WAI) instruction instead. Logically emulates INT, but without triggering a soft interrupt. Note that the NOP instruction maps to BRK, and will not function correctly if this option is set. jshamlet 4692d 04h /
161 synchronize binutils/ with gnu dev tree of 2.21.53.20110828 khays 4715d 23h /
160 synchronize binutils/gas with gnu dev tree of 2.21.53.20110828 khays 4715d 23h /
159 synchronize binutils/gold with gnu dev tree of 2.21.53.20110828 khays 4715d 23h /
158 synchronize binutils/opcodes with gnu dev tree of 2.21.53.20110828 khays 4715d 23h /
157 synchronize binutils/ld with gnu dev tree of 2.21.53.20110828 khays 4715d 23h /
156 Optimized for timing,
Flattened block structure to single entity.
jshamlet 4748d 19h /
155 Fixed additional interrupt logic bug,
Optimized several blocks - including ALU, stack, program counter, and data path.
jshamlet 4749d 14h /
154 Fixed problem with missing data path override in interrupt logic. Should resolve issues with processor crashing when an interrupt occurs as a STO instruction is being executed. jshamlet 4754d 17h /
153 Fixed bug in interrupt logic that caused stack pointer to increment if interrupt occurred as specific instructions were being decoded,
Fixed bug in interrupt logic where instruction caching would remain enabled during an interrupt, causing improper execution depending on what instruction was in the decode stage as the interrupt is trigered.
jshamlet 4781d 12h /
152 Correct the descriptions for GMSK and SMSK instructions in the Open8 Assembly Language Reference khays 4789d 15h /
151 Fixed STO instruction and interrupt logic to avoid address bus corruption issues. jshamlet 4791d 15h /
150 Updated the assembly language reference to add the CLR pseudo-mnemonic khays 4791d 23h /
149 added clr "Clear Accumulator" pseudo-instruction khays 4792d 01h /
148 catch up with binutils trunk through date-version 20110613 khays 4792d 19h /
147 GNU binutils port for Open8 - addition of all remaining files khays 4801d 13h /
146 GNU binutils port for Open8 - addition of gas/testsuite/gas/tic6x files khays 4801d 13h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.