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Rev Log message Author Age Path
21 flakey sim bugs (1/10 test 2 fails) stvhawes 3299d 20h /
20 search_control_sim prepped stvhawes 3306d 15h /
19 search_control is up for simulation (ghdl) - tidied extra testbenches stvhawes 3313d 15h /
18 search_control is up for simulation (ghdl) stvhawes 3313d 15h /
17 persistent bug: search_control_wrapper.vhd:230:21:@36us:(assertion error): search_control_wrapper: test: 3 bad id stvhawes 3319d 02h /
16 minor fixes to search_control test bench stvhawes 3325d 12h /
15 adding in search_control and testbench stvhawes 3326d 17h /
14 search_item_wrapper bench debugged stvhawes 3332d 13h /
13 test bench for search_item stvhawes 3335d 17h /
12 wrapper test for search_item stvhawes 3341d 03h /
11 multiplex searh item added stvhawes 3341d 20h /
10 split source files to sime and rtl stvhawes 3355d 19h /
9 highlevel block diagram added stvhawes 3356d 16h /
8 sim sequence error fixed, so 20% success -> 100% success for unit test on fpga stvhawes 3356d 18h /
7 split clock/byte_ready and fix logic stvhawes 3361d 11h /
6 fixing synthesizable stvhawes 3362d 20h /
5 fixing synthesizable stvhawes 3363d 00h /
4 developing ideas around unit test / fpga verification stvhawes 3363d 12h /
3 developing ideas around unit test / fpga verification stvhawes 3363d 12h /
2 initial sources, wrappers for regression test harness stvhawes 3374d 15h /

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