Rev |
Log message |
Author |
Age |
Path |
20 |
Lots of bug fixes: After turning on XIP, and running in XIP mode, leaving XIP
mode turns it back off again, necessitating a new write to the VCon register.
Further, XIP mode starts in extended SPI mode, and only transfers in QSPI
mode for data. Finally, two new commands have been created: enabling the
SPI memory reset, and actually resetting the SPI memory. In general, these
are all better--as the EQSPI flash controller now works with these changes,
whereby it didn't really work without them before. |
dgisselq |
2951d 00h |
/ |
19 |
Creates an LED mask portion of writing to the LED's register. Only those
bits specified in the mask (bits [7:4]) will be adjusted in the LED
register on a write. Hence to set all on, set the LED register to 0x0ff,
all off, 0x0f0, or to set LED 0 to on while leaving the others unchanged,
set it to 0x011. |
dgisselq |
2951d 00h |
/ |
18 |
The device can now program and configure itself, allowing bootstrap possibilities.
` |
dgisselq |
2951d 00h |
/ |
17 |
Fixed the misaddressed I/O peripherals in the fastio peripheral group. In
particular, UART and GPS were misaddressed. This has now been fixed, so these
peripherals (should) match the spec. Further, the default speed of the two
UARTs has been adjusted to 115200/8N1 for the aux UART, and 9600/8N1 for the
GPS UART. The Aux UART transmitter also passes testing, so at least that one
works. |
dgisselq |
2952d 23h |
/ |
16 |
This returns the scope to its original configuration, where the decode()
function is not allowed to have any side effects. |
dgisselq |
2953d 00h |
/ |
15 |
These files were changed/perfected as part of getting the EQSPI flash driver
up and running. They currently match the hardware, as far as I can tell, and
the test bench (_tb.cpp file) shows that the Verilog modules work (with the
simulated hardware) as designed. |
dgisselq |
2953d 01h |
/ |
14 |
All changes made as a part of getting the flash driver up and running. Today,
it successfully programmed a configuration into the Arty via wbprogram, so ...
that's been my last/best test. |
dgisselq |
2953d 01h |
/ |
13 |
Here are the updates necessary to get the initial Quad SPI flash driver working.
This includes in particular the bus interconnect (in fastmaster.v), and the
final hookup to the external wires (in fasttop.v). |
dgisselq |
2953d 01h |
/ |
12 |
A work in progress. This checkin contains fixes for the flash (mostly),
together with some logic reductions facilitating full speed (200MHz) build. |
dgisselq |
2954d 04h |
/ |
11 |
Files necessary to simulate the entire Arty board--everything at the fastmaster
module and below. |
dgisselq |
2954d 04h |
/ |
10 |
Updated flash data and test files, for a flash that produces it's answers a
clock after I'm expecting them. |
dgisselq |
2954d 04h |
/ |
9 |
Adding copywrite statement (oops). |
dgisselq |
2954d 04h |
/ |
8 |
Fixes the makefile so it builds a complete testbench suite, emulating the
entire Arty board. |
dgisselq |
2954d 04h |
/ |
7 |
This implements the coordination of a massive build/test suite--just not the
actual configuration file itself. |
dgisselq |
2954d 04h |
/ |
6 |
Minor updates, mostly to support the development of the DDR3 SDRAM--such
as creating addresses for the debugging scope used to figure out what's
going on with it. |
dgisselq |
2954d 04h |
/ |
5 |
Initial checkin, this time of the bench testing s/w. |
dgisselq |
2969d 07h |
/ |
4 |
Initial host software pack. |
dgisselq |
2969d 07h |
/ |
3 |
Initial set of files. The flash appears to work, memory hasn't been started,
the MDIO controller works in simulation, etc. Everything below fasttop.v works
at 200MHz (not the CPU---yet). |
dgisselq |
2969d 07h |
/ |
2 |
Initial documentation/proposed specification. (I'm writing the spec as I'm
building the core.) |
dgisselq |
2970d 02h |
/ |
1 |
The project and the structure was created |
root |
2970d 06h |
/ |