OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] - Rev 99

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
99 Small fix for CVER simulator support. olivier.girard 4946d 01h /
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4946d 01h /
97 Update Tools' Windows executables with EraseROM command fix. olivier.girard 4947d 01h /
96 Fixed EraseROM command in the TCL library of the Software development tools. olivier.girard 4947d 01h /
95 Update some test patterns for the additional simulator supports. olivier.girard 4950d 00h /
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4950d 01h /
93 Update Tools' Windows executables. olivier.girard 4954d 00h /
92 Fixed bug where the openmsp430-minidebug application shows data memory size instead of program memory size and program memory size instead of data memory size.
Thanks to "dir" for reporting the bug :-)		 olivier.girard 4954d 01h /
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4954d 01h /
90 Update windows executables for the tools. olivier.girard 4969d 07h /
89 Update the loader tool to support Intel-HEX format. olivier.girard 4969d 07h /
88 Update windows executables for the tools. olivier.girard 4969d 07h /
87 Minor update of gdbproxy to allow sourcing some custom tcl scripts.
Major update of the minidebugger (complete re-work of the GUI).		 olivier.girard 4969d 07h /
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4976d 22h /
85 Diverse RTL cosmetic updates. olivier.girard 4977d 00h /
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4982d 01h /
83 Add Oscilloscope screenshot + link to the original game. olivier.girard 5028d 01h /
82 Update Actel example project:
- synthesis scripts.
- Spacewar demo program.
- SVN ignore patterns for diverse directories		 olivier.girard 5028d 01h /
81 Initial synthesis, P&R setup for the Actel example project. olivier.girard 5030d 23h /
80 Create initial version of the Actel FPGA implementation example. olivier.girard 5031d 08h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.