URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] - Rev 64

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
64	Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile.	julius	5352d 06h	/
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5362d 03h	/
62	This material is part of the separate website downloads directory.	jeremybennett	5373d 06h	/
61	The build directory should not be part of the SVN configuration.	jeremybennett	5373d 06h	/
60	Mark Jarvin's patches to support Mac OS X (Snow Leopard).	jeremybennett	5379d 23h	/
59	Toolchain install script gcc patch change and gdb configure change	julius	5401d 00h	/
58	ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up	julius	5403d 22h	/
57	ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words	julius	5409d 02h	/
56	adding generic pll model to orpsoc	julius	5417d 05h	/
55	Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk	julius	5419d 19h	/
54	wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist	julius	5430d 02h	/
53	Fixed incorrect commandline option for ORPSoC and main makefile setting	julius	5448d 03h	/
52	ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation	julius	5448d 23h	/
51	ORPSoCv2 updates: cycle accurate profiling, ELF loading	julius	5463d 01h	/
50	Adding or32_funcs.S	julius	5463d 05h	/
49	Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update	julius	5481d 19h	/
48	Adds an initialization to keep GCC happy in jp1_ll_read_jp1.	jeremybennett	5481d 22h	/
47	debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions	julius	5491d 05h	/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5497d 06h	/
45	Orpsoc eth test fix and script error message update	julius	5504d 06h	/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories openrisc_me

[/] - Rev 64

Filtering Options