URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 1000

Rev	Log message	Author	Age	Path
1000	IC/DC cache enable routines fixed.	simons	7987d 06h	/
999	Now every ramdisk image should have init program.	simons	7987d 07h	/
998	added missing fout initialization	markom	7987d 08h	/
997	PRINTF should be used instead of printf; command redirection repaired	markom	7987d 09h	/
996	some minor bugs fixed	markom	7988d 08h	/
995	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7988d 16h	/
994	Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.	lampret	7988d 16h	/
993	Fixed IMMU bug.	lampret	7988d 16h	/
992	A bug when cache enabled and bus error comes fixed.	simons	7989d 01h	/
991	Different memory controller.	simons	7989d 01h	/
990	Test is now complete.	simons	7989d 01h	/
989	c++ is making problems so, for now, it is excluded.	simons	7990d 09h	/
988	ORP architecture supported.	simons	7991d 00h	/
987	ORP architecture supported.	simons	7991d 08h	/
986	outputs out of function are not registered anymore	markom	7991d 08h	/
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	7991d 20h	/
984	Disable SB until it is tested	lampret	7991d 20h	/
983	First checkin	lampret	7991d 22h	/
982	Moved to sim/bin	lampret	7991d 22h	/
981	First checkin.	lampret	7991d 22h	/