URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 995

Rev	Log message	Author	Age	Path
995	This commit was manufactured by cvs2svn to create tag 'rel_3'.		8009d 17h	/
994	Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.	lampret	8009d 17h	/
993	Fixed IMMU bug.	lampret	8009d 17h	/
992	A bug when cache enabled and bus error comes fixed.	simons	8010d 02h	/
991	Different memory controller.	simons	8010d 02h	/
990	Test is now complete.	simons	8010d 02h	/
989	c++ is making problems so, for now, it is excluded.	simons	8011d 10h	/
988	ORP architecture supported.	simons	8012d 02h	/
987	ORP architecture supported.	simons	8012d 09h	/
986	outputs out of function are not registered anymore	markom	8012d 09h	/
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	8012d 21h	/
984	Disable SB until it is tested	lampret	8012d 21h	/
983	First checkin	lampret	8012d 23h	/
982	Moved to sim/bin	lampret	8012d 23h	/
981	First checkin.	lampret	8012d 23h	/
980	Removed sim.tcl that shouldn't be here.	lampret	8012d 23h	/
979	Removed old test case binaries.	lampret	8012d 23h	/
978	Added variable delay for SRAM.	lampret	8012d 23h	/
977	Added store buffer.	lampret	8012d 23h	/
976	Added store buffer	lampret	8012d 23h	/