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Rev Log message Author Age Path
17 use logic for $f3m_mux6$ homer.xing 4669d 01h /
16 Add synthesis configuration files homer.xing 4669d 04h /
15 add document. ha ha ha homer.xing 4669d 05h /
14 Move constraint file homer.xing 4669d 06h /
13 Add document and synthesis directories homer.xing 4669d 06h /
12 Simplify the interface of the core. homer.xing 4669d 07h /
11 Cheers! as fast as a rocket homer.xing 4670d 02h /
10 Ho ho, better circuit homer.xing 4670d 21h /
9 Add constrains file for ISE homer.xing 4672d 00h /
8 Finished Tate Pairing. Ha ha ha homer.xing 4672d 01h /
7 Finish inversion @ f33m homer.xing 4680d 06h /
6 add testbench for $f33m$. homer.xing 4681d 06h /
5 rename director : verilog/ -> rtl/ homer.xing 4681d 06h /
4 add testbench homer.xing 4682d 04h /
3 finish Duursma Lee algorithm. doing f33m module homer.xing 4682d 04h /
2 upload code for Duursma-Lee algorithm. I am still developing them. homer.xing 4683d 03h /
1 The project and the structure was created root 4683d 04h /

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