URL https://opencores.org/ocsvn/pairing/pairing/trunk

Subversion Repositories pairing

[/] - Rev 28

Rev	Log message	Author	Age	Path
28	Non-net port XXX cannot be of mode input, when using the "`default_nettype none" to turn off automatic inference of wires in the design. ha ha	homer.xing	4653d 05h	/
27	definition for undefined wire	homer.xing	4653d 06h	/
26	Detailed description for the ModelSim macro file and the main test bench file	homer.xing	4659d 02h	/
25	simulation scripts and readme-file explaining how to start the simulation	homer.xing	4659d 02h	/
24	LGPL claim in each source hdl file	homer.xing	4667d 02h	/
23	LGPL license text	homer.xing	4667d 02h	/
22	Change TAB to space	homer.xing	4667d 04h	/
21	Add detailed input data capture condition in the document	homer.xing	4667d 04h	/
20	Add a module and a testbench for Xilinx ISE post-route simulation	homer.xing	4668d 06h	/
19	Update synthesis result	homer.xing	4669d 00h	/
18	add synthesis result	homer.xing	4669d 00h	/
17	use logic for $f3m_mux6$	homer.xing	4669d 01h	/
16	Add synthesis configuration files	homer.xing	4669d 05h	/
15	add document. ha ha ha	homer.xing	4669d 06h	/
14	Move constraint file	homer.xing	4669d 06h	/
13	Add document and synthesis directories	homer.xing	4669d 06h	/
12	Simplify the interface of the core.	homer.xing	4669d 07h	/
11	Cheers! as fast as a rocket	homer.xing	4670d 03h	/
10	Ho ho, better circuit	homer.xing	4670d 21h	/
9	Add constrains file for ISE	homer.xing	4672d 00h	/