OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] - Rev 80

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
80 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7962d 13h /
79 Updated. mihad 7962d 13h /
78 Old files with wrong names removed. mihad 7962d 13h /
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7962d 13h /
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7965d 13h /
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7968d 14h /
74 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7968d 14h /
73 Bug fixes, testcases added. mihad 7968d 14h /
72 *** empty log message *** mihad 8015d 18h /
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 8023d 10h /
70 This commit was manufactured by cvs2svn to create tag 'rel_2'. 8060d 17h /
69 Changed BIST signal names etc.. mihad 8060d 17h /
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 8064d 03h /
67 Changed BIST signals for RAMs. tadejm 8064d 07h /
66 Changed empty status generation in pciw_fifo_control.v mihad 8067d 18h /
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 8070d 16h /
64 The testcase I just added in previous revision repaired mihad 8070d 18h /
63 Added additional testcase and changed rst name in BIST to trst mihad 8070d 20h /
62 Added BIST signals for RAMs. mihad 8073d 13h /
61 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8081d 13h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.