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Rev Log message Author Age Path
36 Ensure correct read of CSR after stall skordal 3325d 23h /
35 Prevent jumping/branching when stalling skordal 3325d 23h /
34 Prevent flushing the pipeline if it is stalling skordal 3325d 23h /
33 Ensure correct read of CSR after stall skordal 3325d 23h /
32 Prevent jumping/branching when stalling skordal 3328d 20h /
31 Prevent flushing the pipeline if it is stalling skordal 3328d 21h /
30 Add testcase for a combination of instructions that fail when using cache skordal 3331d 02h /
29 Add reset functionality for the WB arbiter state machine skordal 3333d 21h /
28 Add rudimentary User's manual skordal 3339d 20h /
27 Prevent exceptions from being taken while stalling skordal 3339d 22h /
26 Prevent exceptions from being taken while stalling

Jumping to an exception handler while stalling and waiting for a load/store
instruction to finish can cause undefined results from the load/store
instruction. This actually fixes the issue mentioned in revision r20.
skordal 3340d 01h /
25 Add placeholder cache modules and a wishbone arbiter skordal 3342d 06h /
24 Remove unused STRINGIFY macros skordal 3342d 19h /
23 Create branch to use for implementing a cache skordal 3342d 19h /
22 Fix the potato_get_badvaddr() macro skordal 3342d 19h /
21 Upgrade the example design to use a 60 MHz system clock skordal 3342d 19h /
20 Fix SHA256 benchmark crash by storing all registers on exception handler entry

This problem will disappear when the processor is updated to conform to the
new supervisor specification, which will allow us to use a compiler that
conforms to the new "official" ABI.
skordal 3342d 19h /
19 SHA256 benchmark: allow compiler to inline at will skordal 3342d 20h /
18 instr_misalign_check: add do_jump to sensitivity list skordal 3344d 19h /
17 Improve detection of unaligned instructions skordal 3349d 02h /

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