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18 - Read/Write of the CP0 register is in the WB stage, but Exception detection begin from the MEM stage. ameziti 5984d 18h /
17 - UnFonctional Modifications: Change the name of the address port of "CP0". ameziti 5984d 19h /
16 - Remove All generable files from the project. ameziti 5985d 02h /
15 - UnFonctional Modifications.
- Change the "CP0" define to "EXCEPTION".		 ameziti 5985d 04h /
14 Remove unnecessary files from project. ameziti 5985d 11h /
13 - To simplify the exception traitement: Instruction are executed serialy.
- Exception event must be treated CONCURRENTLY with the other event that stall the pipeline.		 ameziti 5985d 11h /
12 To simplify the exception traitement: Instruction are executed serialy. ameziti 5985d 12h /
11 Exception event must be treated CONCURRENTLY with the other event that stall the pipeline. ameziti 5985d 12h /
10 Modification of the CP0. ameziti 5985d 13h /
9 When D-Cache miss, there's no need to stall MEMWB and freeze WB.
The solution is to flush MEMWB only.		 ameziti 5985d 13h /
8 Enhancement of the "Controler specification doc". ameziti 5988d 13h /
7 Add Pipeline Controler specification documentation. ameziti 5989d 11h /
6 When D-Cache miss, there's no need to stall MEMWB and freeze WB.
The solution is to flush MEMWB only.		 ameziti 5989d 13h /
5 Remove the Multiple Arithmetic Unit fonction.
- The Pipeline must stall when Mult/Div unit is busy.
- Whether there's a mflo or mfhi.
- see `define MULTIPLE_ALU		 ameziti 5990d 11h /
4 Add Soc Image in the Specification documentation ameziti 6011d 13h /
3 This commit was manufactured by cvs2svn to create tag 'arelease'. 6012d 22h /
2 First Import the project on the opencores.org CVS server ameziti 6012d 22h /
1 Standard project directories initialized by cvs2svn. 6012d 22h /

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